原因由于颗粒的fly-by结构各信号间走线不齐需要依次去cal目的使WCK与CK对齐行为WCK捕捉CLKDQ feedback值通过扫描WCK delay找到0–1的位置即WCK和CLK对齐的位置注意1需要WCK:CK 2:1WCK toggle 7.5 cycle2tWLO后DQ feedback采样结果DQ[7:0]反馈byte0, DQ[15:8]反馈byte23WCK再次toggle时DQ值unknow一些疑问猜测Q1当WCK:CK在norm r/w是4:1但WCK2CK syn需要2:1是谁的freq变A1如SPEC“The CK frequency may be at any frequency supported by the DRAM. For example, the CK frequency may be 1066MHz for an 8533 data rate device. The WCK frequency is limited to 2 times the CK rate when in WCK2CK Leveling Mode, as 2:1 CKR mode is required” 当频率较高若为了2:1 mode升CK频率而超过颗粒限定时都是选择CK不变WCK2CKQ2LP5在新思的文档中要多加Coarse Write Leveling去调整周期偏移为什么WCK位置会有周期性偏移的风险附LP5 LP4 时序参数附LP4 SPEC tDQSS
原因由于颗粒的fly-by结构各信号间走线不齐需要依次去cal目的使WCK与CK对齐行为WCK捕捉CLKDQ feedback值通过扫描WCK delay找到0–1的位置即WCK和CLK对齐的位置注意1需要WCK:CK 2:1WCK toggle 7.5 cycle2tWLO后DQ feedback采样结果DQ[7:0]反馈byte0, DQ[15:8]反馈byte23WCK再次toggle时DQ值unknow一些疑问猜测Q1当WCK:CK在norm r/w是4:1但WCK2CK syn需要2:1是谁的freq变A1如SPEC“The CK frequency may be at any frequency supported by the DRAM. For example, the CK frequency may be 1066MHz for an 8533 data rate device. The WCK frequency is limited to 2 times the CK rate when in WCK2CK Leveling Mode, as 2:1 CKR mode is required” 当频率较高若为了2:1 mode升CK频率而超过颗粒限定时都是选择CK不变WCK2CKQ2LP5在新思的文档中要多加Coarse Write Leveling去调整周期偏移为什么WCK位置会有周期性偏移的风险附LP5 LP4 时序参数附LP4 SPEC tDQSS
