![verilog HDLBits刷题[Bulid a circuit from a simulation waveform]“Sim/circuit6”---Combinational circuit6](http://pic.xiahunao.cn/yaotu/verilog HDLBits刷题[Bulid a circuit from a simulation waveform]“Sim/circuit6”---Combinational circuit6)
1、题目2、分析a在0-7之间循环每个相同的a对应相同的输出3、代码module top_module ( input [2:0] a, output [15:0] q ); always (*) begin case(a) 0 : q 16h1232; 1 : q 16haee0; 2 : q 16h27d4; 3 : q 16h5a0e; 4 : q 16h2066; 5 : q 16h64ce; 6 : q 16hc526; 7 : q 16h2f19; default : ; endcase end endmodule4、结果
1、题目2、分析a在0-7之间循环每个相同的a对应相同的输出3、代码module top_module ( input [2:0] a, output [15:0] q ); always (*) begin case(a) 0 : q 16h1232; 1 : q 16haee0; 2 : q 16h27d4; 3 : q 16h5a0e; 4 : q 16h2066; 5 : q 16h64ce; 6 : q 16hc526; 7 : q 16h2f19; default : ; endcase end endmodule4、结果
![verilog HDLBits刷题[Bulid a circuit from a simulation waveform]“Sim/circuit7”---Sequential circuit7](http://pic.xiahunao.cn/yaotu/verilog HDLBits刷题[Bulid a circuit from a simulation waveform]“Sim/circuit7”---Sequential circuit7)
