setup/hold check边沿不对的原因

文章目录sdc中设置了set_multicycle_pathlib里面timing arc既有positive_unate又有negative_unateclock的占空比不是50%sdc中设置了set_multicycle_pathsetup multicycle的默认值是1hold multicycle的默认值是0。如下所示pt_shell set_multicycle_path -setup 1 -from ff1/CP -to ff2/Dpt_shell set_multicycle_path -hold 0 -from ff1/CP -to ff2/D下面所示为setup 2 cycle check, hold同沿check.pt_shell set_multicycle_path -setup 2 -from ff1/CP -to ff2/Dpt_shell set_multicycle_path -hold 1 -from ff1/CP -to ff2/D下面所示为setup 1 cycle check, hold向前借一个周期.pt_shell set_multicycle_path -setup 1 -from ff1/CP -to ff2/Dpt_shell set_multicycle_path -hold 1 -from ff1/CP -to ff2/D下面所示为setup 2 cycle check, hold向前借一个周期.pt_shell set_multicycle_path -setup 2 -from ff1/CP -to ff2/Dpt_shell set_multicycle_path -hold 2 -from ff1/CP -to ff2/Dlib里面timing arc既有positive_unate又有negative_unateclock的占空比不是50%可通过report_clock指令reports clock-related information.当setup/hold check边沿不对时可能存在上述的原因具体情况需要具体分析。