verilog HDLBits刷题[Finite State Machines]“Exams/2012 q2b”---Q2b:One-hot FSM equations

1、题目The state diagram for this question is shown again below.Assume that a one-hot code is used with the state assignmenty[5:0] 000001(A), 000010(B), 000100(C), 001000(D), 010000(E), 100000(F)Write a logic expression for the signalY1, which is the input of state flip-flopy[1].Write a logic expression for the signalY3, which is the input of state flip-flopy[3].(Derive the logic equations by inspection assuming a one-hot encoding. The testbench will test with non-one hot inputs to make sure youre not trying to do something more complicated).2、代码module top_module ( input [5:0] y, input w, output Y1, output Y3 ); parameter A6b000001,B6b000010,C6b000100,D6b001000,E6b010000,F6b100000; reg [5:0]next_state; assign next_state[0]y[0](~w)||y[3](~w); assign next_state[1]y[0]w; assign next_state[2]y[1]w||y[5]w; assign next_state[3]y[1](~w)||y[2](~w)||y[4](~w)||y[5](~w); assign next_state[4]y[2]w||y[4]w; assign next_state[5]y[3]w; assign Y1next_state[1]; assign Y3next_state[3]; endmodule