![verilog HDLBits刷题[Building Larger Circuits]“Exams/review2015 count1k”---Counter with period 1000](http://pic.xiahunao.cn/yaotu/verilog HDLBits刷题[Building Larger Circuits]“Exams/review2015 count1k”---Counter with period 1000)
1、题目Build a counter that counts from 0 to 999, inclusive, with a period of 1000 cycles. The reset input is synchronous, and should reset the counter to 0.2、代码module top_module ( input clk, input reset, output [9:0] q); reg [9:0]cnt; always(posedge clk)begin if(reset) cnt10d0; else if(cnt999) cnt10d0; else cntcnt1; end assign qcnt; endmodule
1、题目Build a counter that counts from 0 to 999, inclusive, with a period of 1000 cycles. The reset input is synchronous, and should reset the counter to 0.2、代码module top_module ( input clk, input reset, output [9:0] q); reg [9:0]cnt; always(posedge clk)begin if(reset) cnt10d0; else if(cnt999) cnt10d0; else cntcnt1; end assign qcnt; endmodule
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