verilog HDLBits刷题[Building Larger Circuits]“Exams/review2015 fsmshi”---FSM :Enable shift register

1、题目This is the third component in a series of five exercises that builds a complex counter out of several smaller circuits. See the final exercise for the overall design.As part of the FSM for controlling the shift register, we want the ability to enable the shift register for exactly 4 clock cycles whenever the proper bit pattern is detected. We handle sequence detection in Exams/review2015_fsmseq, so this portion of the FSM only handles enabling the shift register for 4 cycles.Whenever the FSM is reset, assert shift_ena for 4 cycles, then 0 forever (until reset).2、分析说实话我不太理解这个题目觉得题目和所给的时序对不上根据题目“Whenever the FSM is reset, assert shift_ena for 4 cycles, then 0 forever (until reset).”我会以为是复位开始的四个周期为高看了网上其它答案才发现原来是复位有效使能shift_ena为高复位无效后使能shift_ena为高四个时钟周期之后如果复位还是无效那么shift_ena将保持为03、代码module top_module ( input clk, input reset, output reg shift_ena ); reg [1:0] cnt; always (posedge clk) begin if(reset) begin cnt 2b00; shift_ena 1b1; end else if(cnt 2d3) begin shift_ena 1b0; cnt cnt; end else begin shift_ena 1b1; cnt cnt 1b1; end end endmodule